San Jose, CA - Nov 13
Salary: $110,000 to $140,000 per year
... ASICs. DSP algorithm Verilog implementation tradeoff analysis Spec, architect, RTL coding, behavioural modeling, synthesis/simulation, verification, etc. SOC Design using ARM system Technical Requirements 5+ yrs experience in DSP algorithm Verilog RTL implementation, digital ASIC design, behavioral modeling and verification of DSP functions Experience developing system / ...